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A49LF040A
Preliminary
Document Title 4 Mbit CMOS 3.3 Volt-only Low Pin Count Flash Memory Revision History
Rev. No.
0.0 0.1
4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
History
Initial issue Correct the part number from A49LF040A to A49LF040AT on page 29
Issue Date
March 3, 2006 March 28, 2006
Remark
Preliminary
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Preliminary
FEATURES
* Single Power Supply Operation Low voltage range: 3.0 V - 3.6 V for Read and Write Operations * Standard Intel Low Pin Count Interface Read compatible to Intel(R) Low Pin Count (LPC) interface * Memory Configuration 512K x 8 (4 Mbit) * Block Architecture 4Mbit: eight uniform 64KByte blocks Supports full chip erase for Address/Address Multiplexed (A/A Mux) mode * Automatic Erase and Program Operation Embedded Byte Program and Block/Chip Erase algorithms Typical 10 s/byte programming time Typical 1s block erase time * Two Operational Modes Low Pin Count Interface (LPC) Mode for in-system operation Address/Address Multiplexed (A/A Mux) Interface Mode for programming equipment * Low Pin Count (LPC) Mode 33 MHz synchronous operation with PCI bus 5-signal communication interface for in-system read and write operations Standard SDP Command Set Data Polling (I/O7) and Toggle Bit (I/O6) features Block Locking Register for all blocks 4 ID pins for multi-chip selection 5 GPI pins for General Purpose Input Register TBL pin for hardware write protection to Boot Block WP pin for hardware write protection to whole memory array except Boot Block * Address/Address Multiplexed (A/A Mux) Mode 11-pin multiplexed address and 8-pin data I/O interface Supports fast programming on EPROM programmers Standard SDP Command Set Data Polling (I/O7) and Toggle Bit (I/O6) features * Lower Power Consumption Typical 12mA active read current Typical 24mA program/erase current * High Product Endurance Guarantee 100,000 program/erase cycles for each block Minimum 20 years data retention * Compatible Pin-out and Packaging 32-pin (8 mm x 14 mm) TSOP (TYPE I) 32-pin PLCC Optional Pb-free (Lead-free) package All Pb-free (Lead-free) products are RoHS compliant
4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory
General Description
The A49LF040A flash memory device is designed to be read-compatible with the Intel Low Pin Count (LPC) Interface Specification 1.1. This device is designed to use a single low voltage, range from 3.0 Volt to 3.6 Volt power supply to perform in-system or off-system read and write operations. It provides protection for the storage and update of code and data in addition to adding system design flexibility through five general-purpose inputs. Two interface modes are supported by the A49LF040A: Low Pin Count (LPC) Interface mode for In-System programming and Address/Address Multiplexed (A/A Mux) mode for fast factory programming of PC-BIOS applications. The memory is divided into eight uniform 64Kbyte blocks that can be erased independently without affecting the data in other blocks. Blocks also can be protected individually to prevent accidental Program or Erase commands from modifying the memory. The boot block can be write protected by a hardware method controlled by the TBL pin or a register-based protection turned on/off by the Block Locking Registers (LPC mode only). The rest of blocks except boot block in the device also can be write protected by WP pin or Block Locking Registers (LPC mode only). The Program and Erase operations are executed by issuing the Program/Erase commands into the command interface by which activating the internal control logic to automatically process the Program/Erase procedures. The device can be programmed on a byte-by-byte basis after performing the Erase operation. In addition to the Block Erase operation, the Chip Erase feature is provided in A/A Mux mode that allows the whole memory to be erased in one single Erase operation. The A49LF040A provides the status detection such as Data Polling (I/O7) and Toggle Bit (I/O6) Functions in both FWH/LPC and A/A Mux modes. The process or completion of Program and Erase operations can be detected by reading the status bits. The A49LF040A is offered in 32-lead TSOP and 32-lead PLCC packages with optional environmental friendly leadfree package. See Figures 1 and 2 for pin assignments and Table 1 for pin descriptions.
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A49LF040
Pin Configurations Figure 1: Pin Assignments for 32-Lead PLCC
LCLK R/C GPI2 GPI3 LPC GPI4 A10 VDD VDD RST RST NC NC
A/A MUX
A8
LPC GPI1 GPI0 WP TBL ID3 ID2 ID1 ID0 LAD0
A/A MUX A7 A6 A5 A4 A3 A2 A1 A0 I/O0
A9
5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 13
29 28 27
A/A MUX MODE VSS NC NC VDD OE WE R/B I/O7
32
31
30
4
3
2
1
LPC MODE VSS NC NC VDD INIT LFRAME RES RES
32-lead PLCC Top View
26 25 24 23 22 21
A/A MUX
VSS
I/O1
I/O2
I/O3
I/O4 RES
I/O5 RES
LAD1
LAD2
LAD3
Figure 2: Pin Assignments for 32-Lead TSOP
LPC NC NC NC VSS MODE GPI4 LCLK VDD NC RST GPI3 GPI2 GPI1 GPI0 WP TBL A/A MUX NC NC NC VSS MODE A10 R/C VDD NC RST A9 A8 A7 A6 A5 A4 A/A MUX OE WE VDD I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 LPC INIT LFRAME VDD RES RES RES RES LAD3 VSS LAD2 LAD1 LAD0 ID0 ID1 ID2 ID3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
RES
VSS
LPC
I/O6
32-lead TSOP (8MM X 14MM) Top View
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
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A49LF040A
Block Diagram
WP TBL INIT LAD[3:0] LCLK LFRAME ID[3:0] GPI[4:0] A[10:0] I/O7 ~ I/O0 WE OE R/C Mode RST A/A Mux Mode Interface High Voltage Generator Data Latch FWH/LPC Mode Interface Control Logic Input/Output Buffers
R/B Address Latch
Y-Decoder
Y-Gating
X-decoder
Cell Matrix
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A49LF040A
Table 1: Pin Description
Interface A/A Mux LPC X X X X
Symbol A10-A0 I/O7-I/O0 OE
WE
Pin Name Address Data Output Enable Write Enable Interface Mode Select
Type IN I/O IN IN
Descriptions Inputs for addresses during Read and Write operations in A/A Mux mode. Row and column addresses are latched by R/ C pin. To output data during Read cycle and receive input data during Write cycle in A/A Mux mode. The outputs are in tri-state when OE is high. To control the data output buffers. To control the Write operations. To determine which interface is operational. When held high, A/A Mux mode is enabled and when held low, LPC mode is enabled. This pin must be setup at power-up or before return from reset and not change during device operation. This pin is internally pulled down with a resistor between 20-100 K This is the second reset pin for in-system use. INIT and RST pins are internally combined and initialize a device reset when driven low. These four pins are part of the mechanism that allows multiple LPC devices to be attached to the same bus. To identify the component, the correct strapping of these pins must be set. The boot device must have ID[3:0]=0000 and it is recommended that all subsequent devices should use sequential up-count strapping. These pins are internally pulled down with a resistor between 20100 K. These individual inputs can be used for additional board flexibility. The state of these pins can be read immediately at boot, through LPC internal registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated.
MODE
IN
X
X
INIT
Initialize
IN
X
ID[3:0]
Identification Inputs
IN
X
GPI[4:0]
General Purpose Inputs
IN
X
TBL LAD[3:0] LCLK LFRAME RST WP R/ C
Top Block Lock LPC Interface I/Os Clock Frame Reset Write Protect Row/Column Select Ready/Busy Reserved Power Supply Ground No Connection
IN I/O IN IN IN IN IN OUT X X X
X X X X X X
To prevent any write operations to the Boot Block when driven low, regardless of the state of the block lock registers. When TBL is high it disables hardware write protection for the top Boot Block. This pin cannot be left unconnected. I/O Communications in LPC mode. To provide a clock input to the device. This pin is the same as that for the PCI clock and adheres to the PCI specifications. To indicate start of a data transfer operation. LFRAME is also used to abort an LPC cycle in progress. To reset the operation of the device When low, prevents any write operations to all but the highest addressable block. When WP is high it disables hardware write protection for these blocks. This pin cannot be left unconnected. This pin determines whether the address pins are pointing to the row addresses or the column addresses in A/A Mux mode. This pin is used to determine if the device is busy in write operations. Valid only in A/A Mux mode.
R/B
RES VDD VSS NC
X PWR PWR X X X X X X
Reserved. These pins must be left unconnected. To provide power supply (3.0-3.6Volt). Circuit ground. All VSS pins must be grounded. Unconnected pins.
Notes: IN=Input, OUT=output, I/O=Input/Output, PWR=Power
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A49LF040A
Absolute Maximum Ratings*
Temperature Under Bias . . . . . . . . . .. . . . -55C to + 125C Storage Temperature . . . . . . . . . . . . . . . . . -65C to + 125C D.C. Voltage on Any Pins with Respect to Ground (1) . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . -0.5V to VDD + 0.5V Package Power Dissipation Capability (Ta=25C) . . . . . . . . . . . . . . . . . . . . . . . . .... . . . . . -0.5V to VDD + 0.5V Output Short Circuit Current (2) . . . . . . . . . . . . . . . . . 50mA
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specifications are not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VDD + 0.5V. During voltage transitions, input or I/O pins may overshoot to VDD + 2.0V for periods up to 20ns. 2. No more than one output is shorted at a time. Duration of the short circuit should not be greater than one second.
Operating Ranges Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . 0C to +85C VDD Supply Voltages VDD for all devices . . . . . . . . . . . . . . . . . . . . +3.0V to +3.6V Operating ranges define those limits between which the functionally of the device is guaranteed.
MODE SELECTION
The A49LF040A flash memory devices can operate in two distinct interface modes: the Low Pin Count Interface (LPC) mode and the Address/Address Multiplexed (A/A Mux) mode. The Mode pin is used to set the interface mode selection. If the Mode pin is set to logic High, the device is in A/A Mux mode; while if the Mode pin is set Low, the device is in the LPC mode. The Mode pin must be configured prior to device operation. The Mode pin is internally pulled down if the pin is not connected. In LPC mode, the device is configured to interface with its host using Intel's Low Pin Count proprietary protocol. Communication between Host and the A49LF040A occurs via the 4-bit I/O communication signals, LAD[3:0] and the LFRAME . In A/A Mux mode, the device is programmed via an 11-bit address A10-A0 and an 8-bit data I/O7-I/O0. The address inputs are multiplexed in row and column selected by control signal R/ C pin. The column addresses are mapped to the higher internal addresses, and the row addresses are mapped to the lower internal addresses. See the Device Memory Maps in Figure 3 for address assignment.
LPC Read Operation
LPC Read operations read from the memory cells or specific registers in the LPC device. A valid LPC Read operation starts when LFRAME is Low as LCLK rises and a START value "0000b" is on LAD[3:0] then the next nibble "010X" is on LAD[3:0]. Addresses and data are transferred to and from the device decided by a series of "fields". Field sequences and contents are strictly defined for LPC Read operations. Refer to Table 2 for LPC Read Cycle Definition.
LPC Write Operation
LPC Write operations write to the LPC Interface or LPC registers. A valid LPC Write operation starts when LFRAME is Low as LCLK rises and a START value "0000b" is on LAD[3:0] then the next nibble "011X" is on LAD[3:0]. Addresses and data are transferred to and from the device decided by a series of "fields". Field sequences and contents are strictly defined for LPC Write operations. Refer to Table 3 for LPC write Cycle Definition.
LPC MODE OPERATION
The LPC interface consists of four data signals (LAD[3:0]), one control signal ( LFRAME ) and a clock (LCLK). The data signals, control signal and clock comply with PCI specifications. Operations such as Memory Read and Memory Write use Intel LPC propriety protocol. JEDEC Standard SDP (Software Data Protection) Byte-Program and Block-Erase command sequences are incorporated into the LPC memory cycles. Chip-Erase command is only available in A/A Mux mode. The addresses and data are transferred through LAD[3:0] synchronized with the input clock LCLK during a LPC memory cycle. The pulse of LFRAME is inserted for at least one clock period to indicate the start of a LPC memory cycle. The address or data on LAD[3:0] is latched on the rising edge of LCLK. The device enters standby mode when LFRAME is high and no internal operation is in progress. The device is in ready mode when LFRAME is low and no activity is on the LPC bus.
LPC Abort Operation
If LFRAME is driven low for one or more clock cycles during a LPC cycle, the cycle will be terminated and the device will wait for the ABORT command. The host may drive the LAD[3:0] with "1111b" (ABORT command) to return the device to Ready mode. If abort occurs during a Write operation such as checking the operation status with Data Polling (I/O7) or Toggle Bit (I/O6) pins, the read status cycle will be aborted but the internal write operation will not be affected. In this case, only the reset operation initiated by RST or INIT pin can terminate the Write operation.
Response To Invalid Fields
During LPC operations, the LPC will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows:
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A49LF040
Table 2: LPC Read Cycle
Clock Cycle Field Name Field Contents LAD[3:0]1 LAD[3:0] Direction Comments
1
START CYCTYPE
0000
IN
LFRAME must be active (low) for the part to respond. Only the last start field (before LFRAME transitioning high) should be recognized. Indicates the type of cycle. Bits 3:2 must be "01b" for memory cycle. Bit 1 indicates the type of transfer "0" for Read. Bit 0 is reserved. Address Phase for Memory Cycle. LPC protocol supports a 32-bit address phase. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. See Table 4 for address bits definition and Table 5 for valid memory address range. In this clock cycle, the host has driven the bus to all 1s and then floats the bus. This is the first part of the bus "turnaround cycle."
2 + DIR
010X
IN
3-10
ADDRESS
YYYY
IN
IN 11 TAR0 1111 Then Float Float 12 TAR1 1111(float) Then OUT 13 14 15 SYNC DATA DATA 0000 ZZZZ ZZZZ OUT OUT OUT OUT 16 TAR0 1111 Then Float Float 17 TAR1 1111(float) Then IN
The A49LF040A takes control of the bus during this cycle.
The A49LF040A outputs the value "0000b" indicating that data will be available during the next clock cycle. This field is the least-significant nibble of the data byte. This field is the most-significant nibble of the data byte. In this clock cycle, the A49LF040A drives the bus to all `1's and then floats the bus. This is the first part of the bus "turnaround cycle".
Host resumes control of the bus during this cycle.
1. Field contents are valid on the rising edge of the present clock cycle.
LPC Single-Byte Read Waveforms
1 LCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
START CYCTYPE + DIR
ADDRESS
TAR0
TAR1
SYNC
DATA
TAR0
TAR1
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Table 3: LPC Write Cycle
Clock Cycle Field Name Field Contents LAD[3:0]1 LAD[3:0] Direction Comments
1
START CYCTYPE
0000
IN
LFRAME must be active (low) for the part to respond. Only the last start field (before LFRAME transitioning high) should be recognized. Indicates the type of cycle. Bits 3:2 must be "01b" for memory cycle. Bit 1 indicates the type of transfer "1" for Write. Bit 0 is reserved. Address Phase for Memory Cycle. LPC protocol supports a 32-bit address phase. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. See Table 4 for address bits definition and Table 5 for valid memory address range. This field is the least-significant nibble of the data byte. This field is the most-significant nibble of the data byte. In this clock cycle, the host has driven the bus to all `1's and then floats the bus. This is the first part of the bus "turnaround cycle." The A49LF040A takes control of the bus during this cycle. The A49LF040A outputs the values "0000b", indicating that it has received data or a flash command. In this clock cycle, the A49LF040A has driven the bus to all `1's and then floats the bus. This is the first part of the bus "turnaround cycle." Host resumes control of the bus during this cycle.
2 + DIR
011X
IN
3-10
ADDRESS
YYYY
IN
11 12 13 14 15
DATA DATA TAR0 TAR1 SYNC
ZZZZ ZZZZ 1111 1111(float) 0000
IN IN IN then Float Float then OUT OUT OUT then Float Float then IN
16 17
TAR0 TAR1
1111 1111(float)
1. Field contents are valid on the rising edge of the present clock cycle.
LPC Write Waveforms
1 LCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
START CYCTYPE + DIR
ADDRESS
DATA
TAR0
TAR1
SYNC
TAR0
TAR1
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A49LF040A
Address out of range: The A49LF040A will only response to address range as specified in Table 4. Address A22 has the special function of directing reads and writes to the flash memory (A22=1) or to the register space (A22=0). ID mismatch: The A49LF040A will compare ID bits in the address field with the hardware ID strapping. If there is a mismatch, the device will ignore the cycle. Refer to Table 6 Multiple Device Selection Configuration for detail. Write Operation Status Detection
Device Memory Hardware Write Protection
The Top Boot Lock ( TBL ) and Write Protect ( WP ) pins are provided for hardware write protection of device memory in the A49LF040A. The TBL pin is used to write protect the top boot block (64 Kbytes) at the highest flash memory address range for the A49LF040A. WP pin write protects the remaining blocks in the flash memory. An active low signal at the TBL pin prevents Program and Erase operations of the top boot block. When TBL pin is held high, write protection of the top boot block is then determined by the Boot Block Locking register. The WP pin serves the same function for the remaining blocks of the device memory. The TBL and WP pins write protection functions operate independently of one another. Both TBL and WP pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL or WP pin during a Program or Erase operation could cause unpredictable results. TBL and WP pins cannot be left unconnected. TBL is internally ORed with the top Boot Block Locking register. When TBL is low, the top Boot Block is hardware write protected regardless of the state of the WriteLock bit for the Boot Block Locking register. Clearing the Write-Lock bit in the register when TBL is low will have no functional effect, even though the register may indicate that the block is no longer locked. WP is internally ORed with the Block Locking register. When WP is low, the blocks are hardware write protected regardless of the state of the WriteLock bit for the corresponding Block Locking registers. Clearing the Write-Lock bit in any register when WP is low will have no functional effect, even though the register may indicate that the block is no longer locked.
The A49LF040A device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data Polling (I/O7) and Toggle Bit (I/O6). The End-of-Write detection mode is incorporated into the LPC Read cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either I/O7 or I/O6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Data Polling (I/O7)
When the A49LF040A device is in the internal Program operation, any attempt to read I/O7 will produce the complement of the true data. Once the Program operation is completed, I/O7 will produce true data. Note that even though I/O7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read I/O7 will produce a `0'. Once the internal Erase operation is completed, I/O7 will produce a `1'. Proper status will not be given using Data Polling if the address is in the invalid range.
Toggle Bit (I/O6)
During the internal Program or Erase operation, any consecutive attempts to read I/O6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop.
Reset
A VIL on INIT or RST pin initiates a device reset. INIT and RST pins have the same function internally. It is required to drive INIT or RST pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT or RST pins low deselects the device and places the output drivers, LAD[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase operation. See Table 19, Reset Timing Parameters for more information. A device reset during an active Program or Erase will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete Erase or Program operation. In this case, the device can take up to TRSTE to abort a Program or Erase operation. PRELIMINARY (March, 2006, Version 0.1) 8
Multiple Device Selection
The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID strapping in a system. When the A49LF040A is used as a boot device, ID[3:0] must be strapped as 0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). The ID bits in the address field are inverse of the hardware strapping. The address bits [A23, A21:A19] for A49LF004 are used to select the device with proper IDs. See Table 6 for IDs. The A49LF040A will compare the strapping values, if there is a mismatch, the device will ignore the remainder of the cycle and go into standby mode. Since there is no ID support in A/A Mux mode, to program multiple devices a stand-alone PROM programmer is recommended.
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REGISTERS
There are two types of registers available on the A49LF040A, the General Purpose Inputs Register, and the JEDEC ID Registers. These registers appear at their respective address location in the 4 GByte system memory map. Unused register locations will read as 00H. Any attempt to read or write any register during an internal Write operation will be ignored. Refer to Table 7 for the LPC register memory map.
Write-Lock. The Write-Lock Bit determines whether the contents of the Block can be modified (using the Program or Erase Command). When the Write-Lock Bit is set to `1', the block is write protected; any operations that attempt to change the data in the block will fail and the Status Register will report the error. When the Write-Lock Bit is reset to `0', the block is not write protected through the Locking Register and may be modified unless write protected through some other means. If Top Block Lock, TBL , is Low, VIL, then the Top Block (Block 7) is write protected and cannot be modified. Similarly, if Write Protect, WP , is Low, VIL, then the Main Blocks (Blocks 0 to 6) are write protected and cannot be modified. After power-up or reset the Write-Lock Bit is always set to `1' (write protected). Read-Lock. The Read-Lock bit determines whether the contents of the Block can be read (from Read mode). When the Read-Lock Bit is set to `1', the block is read protected; any operation that attempts to read the contents of the block will read 00h instead. When the Read-Lock Bit is reset to `0', read operations in the Block return the data programmed into the block as expected. After power-up or reset the ReadLock Bit is always reset to `0' (not read protected). Lock-Down. The Lock-Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock-Down Bit is set to `1', further modification to the Write-Lock, Read-Lock and Lock-Down Bits cannot be performed. A reset or power-up is required before changes to these bits can be made. When the LockDown Bit is reset to `0', the Write-Lock, Read-Lock and LockDown Bits can be changed.
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the A49LF040A. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. See Table 8 for the GPI_REG bits and function, and Table 7 for memory address locations for its respective device strapping.
Table 8: General Purpose Inputs Register
Bit Bit Name Function Pin Number 32-PLCC 32-TSOP
7:5 4 3 2 1 0
GPI[4] GPI[3] GPI[2] GPI[1] GPI[0]
Reserved GPI_REG Bit 4 GPI_REG Bit 3 GPI_REG Bit 2 GPI_REG Bit 1 GPI_REG Bit 0
30 3 4 5 6
6 11 12 13 14
JEDEC ID Registers Block Locking Registers
A49LF040A provides software controlled lock protection through a set of Block Locking registers. The Block Locking Registers are read/write registers and it is accessible through standard addressable memory locations specified in Table 7. See Table 9 for Bit definition of the Block Lock Register.
The JEDEC ID registers identify the device as A49LF040A and manufacturer as AMIC in LPC mode. See Table 7 for memory address locations for its respective JEDEC ID location.
Table 4: Address Bit Definition
A31:A23 A23 A22 A21:A19 A18:A0
1111 1111b
ID[3]
1 = Memory access 0 = Register access
ID[2:0]
Device memory address
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Table 5: Address Decoding Range
ID Strapping Device Access A21:A19 Memory Size
Device #0 - 7 Device #8 - 15
Memory Access Register Access Memory Access Register Access
FFFF FFFFH: FFC0 0000H FFBF FFFFH: FF80 0000H FF7F FFFFH: FF40 0000H FF3F FFFFH: FF00 0000H
4 MByte 4 MByte 4 MByte 4 MByte
Table 6: Multiple Device Selection Configurations
Device# Hardware Strapping ID[3:0] Address Bits Decoding A23 A21 A20 A19
0 (Boot device) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Table 7: LPC Register Memory Map (Boot Device)
Memory Address Mnemonic Register Name Default Type
FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h FFBC0100h FFBC0000h FFBC0001h FFBC0003h
T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK GPI_REG MANUF_REG DEV_REG CONT_REG
Top Block Lock Register (Block 7) Top Block [-1] Lock Register (Block 6) Top Block [-2] Lock Register (Block 5) Top Block [-3] Lock Register (Block 4) Top Block [-4] Lock Register (Block 3) Top Block [-5] Lock Register (Block 2) Top Block [-6] Lock Register (Block 1) Top Block [-7] Lock Register (Block 0) LPC General Purpose Input Register Manufacturer ID Register Device ID Register Continuation ID Register
01h 01h 01h 01h 01h 01h 01h 01h N/A 37h 9Dh 7Fh
R/W R/W R/W R/W R/W R/W R/W R/W R R R R
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Table 9: Lock Register Bit Definition
Data Reserved Bit 7:3 Read-Lock Bit 2 Lock-Down Bit 1 Write-Lock Bit 0 Function
00h 01h 02h 03h 04h 05h 06h 07h
00000 00000 00000 00000 00000 00000 00000 00000
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Full Access. Write locked. Default state at power-up. Locked open (full access locked down). Write-locked down. Read locked. Read and Write locked. Read-locked down Read- and Write-locked down
Data
Function Reserved Read-Lock
7:3 2
1 = Prevents read operations in the block where set 0 = Normal operation for reads in the block where clear. This is the default state.
Lock-Down
1 = Prevents further set or clear operations to the Write-Lock and Read-Lock bits. Lock-Down only can be set 1 but not clear. The block will remain lock-down until reset (with RST or INIT being Low), or until the device is power-on reset. 0 = Normal operation for Write-Lock and Read-Lock bit altering in the block where clear. This is the default state.
Write-Lock
0
1 = Prevents program or erase operations in the block where set. This is the default state. 0 = Normal operation for programming and erase in the block where clear.
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ADDRESS/ADDRESS MULTIPLEXED (A/A MUX) MODE Device Operation
Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE . During the software command sequence the row address is latched on the falling edge of R/ C and the column address is latched on the rising edge of R/ C . Refer to Table 10 and Table 11 for operation modes and the command sequence.
Byte-Program Operation
The A49LF040A device is programmed on a byte-by-byte basis. Before programming, one must ensure that the block, in which the byte which is being programmed exists, is fully erased. The Byte-Program operation is initiated by executing a four-byte command load sequence for Software Data Protection with address and data in the last byte sequence. During the Byte-Program operation, the row address (A10-A0) is latched on the falling edge of R/ C and the column Address (A18-A11) is latched on the rising edge of R/ C . The data bus is latched in the rising edge of WE . See Figure 11 for Program operation timing diagram, Figure 14 for timing waveforms, and Figure 19 for its flowchart. During the Program operation, the only valid reads are Data Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
Read
The Read operation of the A49LF040A device is controlled by OE . OE is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 10 for further details.
Reset
A VIL on RST pin initiates a device reset. Table 10: A/A Mux Mode Operation Selection
Mode
RST
VIH VIH VIH VIH VIL VIH
OE
VIL VIH VIH VIH X VIL
WE
VIH VIL VIH X X VIH
Address
I/O
Read Write Standby Output Disable Reset Product Identification
AIN AIN X X X A18 - A2 = X, A1 = VIL, A0 = VIL A18 - A2 = X, A1 = VIL, A0 = VIH A18 - A2 = X, A1 = VIH, A0 = VIH
DOUT DIN High Z High Z High Z Manufacturer ID Device ID Continuation ID
Block-Erase Operation
The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for the A49LF040A. The Block-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Block-Erase command (30H or 50H) and block address. The internal Block-Erase operation begins after the sixth WE pulse. The End-of-Erase can be determined using either Data Polling or Toggle Bit methods. See Figure 15 for timing waveforms. Any commands written during the Block- Erase operation will be ignored.
Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE . During the internal Erase operation, the only valid read is Toggle Bit or Data Polling. See Table 11 for the command sequence, Figure 16 for timing diagram, and Figure 21 for the flowchart. Any commands written during the Chip-Erase operation will be ignored.
Write Operation Status Detection
The A49LF040A device provides two software means to detect the completion of a Write cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data Polling (I/O7) and Toggle Bit (I/O6). The End-of-Write detection mode is enabled after the rising edge of WE which initiates the internal Write operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle.
Chip-Erase
The A49LF040A device provides a Chip-Erase operation only in A/A Mux mode, which allows the user to erase the entire memory array to the `1's state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six-byte Software Data
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If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either I/O7 or I/O6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. In addition to I/O6 and I/O7 to detect the write status, a R/B pin is also available to detect the end of a Program or Erase operation. R/B is actively pulled low (VIL) during the internal write cycles and is released to high (VIH) at the completion of the cycle.
Hardware Data Protection
Noise/Glitch Protection: A WE pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE low, WE high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
Data Polling (I/O7)
When the A49LF040A device is in the internal Program operation, any attempt to read I/O7 will produce the complement of the true data. Once the Program operation is completed, I/O7 will produce true data. Note that even though I/O7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read I/O7 will produce a `0'. Once the internal Erase operation is completed, I/O7 will produce a `1'. The Data Polling is valid after the rising edge of fourth WE pulse for Program operation. For Block- or Chip-Erase, the Data Polling is valid after the rising edge of sixth WE pulse. See Figure 12 for Data Polling timing diagram. Proper status will not be given using Data Polling if the address is in the invalid range.
Toggle Bit (I/O6)
The A49LF040A provides the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequences. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of a six-byte load sequence. The A49LF040A device is shipped with the Software Data Protection permanently enabled. See Table 11 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within TRC.
Electrical Specifications
The AC and DC specifications for the LPC Interface signals (LAD[3:0], LCLK, LFRAME , and RST ) as defined in Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1. Refer to Table 12 for the DC voltage and current specifications. Refer to the specifications on Table 12 to Table 22 for Clock, Read/Write, and Reset operations.
Product Identification
The product identification mode identifies the Manufacturer ID, Continuation ID, and Device ID of the A49LF040A. See Table 10 for detail information.
During the internal Program or Erase operation, any consecutive attempts to read I/O6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE pulse for Program operation. For Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE pulse. See Figure 13 for Toggle Bit timing diagram.
Data Protection
The A49LF040A device provides both hardware and software features to protect nonvolatile data from inadvertent writes.
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Figure 3: System Memory Map and Device Memory Map for A49LF040A
D Visio.Drawing.6 |
A49LF040A Block 7 (64K Bytes) Block 6 (64K Bytes) Block 5 (64K Bytes) Block 4 (64K Bytes) Block 3 (64K Bytes) Block 2 (64K Bytes) Block 1 (64K Bytes) Block 0 (64K Bytes)
Device Memory 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
Table 11: Software Data Protection Command Definition
Command Block Erase Chip Erase
(3)
Bus Cycles 6 6 4 3 1 3
1 Cycle Addr
(2)
st
(1)
2
nd
Cycle Data
55H 55H 55H 55H
3 Cycle Addr
YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H
rd
4 Cycle Addr
YYYY 5555H YYYY 5555H PA
(6)
th
5 Cycle Addr
YYYY 2AAAH YYYY 2AAAH
th
6 Cycle Addr
BA(4) YYYY 5555H
th
Data
AAH AAH AAH AAH F0H AAH
Addr
YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH
Data
80H 80H A0H 90H
Data
AAH AAH PD
(6)
Data
55H 55H
Data
30H/50H(5) 10H
YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H XXXX XXXXH YYYY 5555H
Byte Program Product ID Entry Product ID Exit Product ID Exit
(7) (7)
YYYY 2AAAH
55H
YYYY 5555H
F0H
Notes: 1. LPC Mode uses consecutive Write cycles to complete a command sequence; A/A Mux Mode uses consecutive bus cycles to complete a command sequence. 2. YYYY = A[31:16]. In LPC mode, during SDP command sequence, YYYY must be within memory address range specified in Table 5. In A/A Mux mode, YYYY can be VIL or VIH, but no other value. 3. Chip erase is available in A/A Mux Mode only. 4. BA: Block Erase Address. 5. Either 30H or 50H are acceptable for Block Erase. 6. PA: Program Byte Address; PD: Byte data to be programmed. 7. Both Product ID Exit commands are equivalent.
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Operating Range Range Ambient Temperature VDD AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 3ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . CL = 30pF
Commercial
0C to +85C
3.0-3.6V
Table 12: DC Operating Characteristics (All Interfaces)
Limits Symbol Parameter Min Max Units Test Conditions
Active VDD Current: IDD Read Active VDD Current: Write ISB IRY(2) II ILI ILO VIHI(3) VILI(3) VIH VIL VOL VOH
(1)
12 24 100 10 100 1 1 1.0 -0.5 0.5VDD -0.5 0.9VDD VDD+0.5 0.4 VDD+0.5 0.3VDD 0.1VDD
mA mA
A
Address Input=VIL/VIH, at F=1/TRCMin, VDD=VDDMax(A/A Mux Mode) OE =VIH, WE =VIH LFRAME =0.9VDD, f=33MHz, VDD=VDDMax, All other inputs 0.9VDD or 0.1VDD LFRAME =VIL, f=33MHz, VDD=VDDMax, All other inputs 0.9VDD or 0.1VDD VIN=0V to VDD, VDD=VDDMax VIN=0V to VDD, VDD=VDDMax VOUT=0V to VDD, VDD=VDDMax VDD=VDDMax VDD=VDDMin VDD=VDDMax VDD=VDDMin IOL=1500A, VDD=VDDMin IOH=-500A, VDD=VDDMin
Standby VDD Current (LPC Mode) Ready Mode VDD Current (LPC Mode) Input Current for Mode and ID[3:0] Pins Input Leakage Current Output Leakage Current
INIT Input High Voltage INIT Input Low Voltage
mA
A A A
V V V V V V
Input High Voltage Input Low Voltage Output Low Voltage Output High Voltage
Notes: 1. IDD active while Erase or Program is in progress. 2. The device is in Ready Mode when no activity is on the LPC bus. 3. Do not violate processor or chipset specification regarding INIT voltage.
Table 13: Recommended System Power-Up Timings
Symbol Parameter Min Units s s
TPU-READ(1) TPU-WRITE
(1)
Power-up to Read Operation Power-up to Write Operation
100 100
Notes: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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Table 14: Pin Impedance (VDD=3.3V, Ta=25C, f=1MHz, other pins open)
Parameter Description Test Condition Max
CI/O (1) CIN
(1)
I/O Pin Capacitance Input Capacitance Pin Inductance
VI/O = 0V VIN = 0V
12pF 12pF 20nH
LPIN (2)
Notes: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI specifications.
Table 15: Clock Timing Parameters
Symbol Parameter Min Max Units
TCYC THIGH TLOW
LCLK Cycle Time LCLK High Time LCLK Low Time LCLK Slew Rate (peak-to-peak)
30 11 11 1 4
ns ns ns V/ns
Figure 4: LCLK Waveform
TCYC THIGH 0.6 VDD 0.5 VDD 0.4 VDD 0.3 VDD 0.2 VDD 0.4 VDD Peak-to-Peak (Min) TLOW
Table 16: LPC Mode Read/Write Cycle Timing Parameters, VDD=3.0-3.6V
Symbol
TSU TDH TVAL TON TOFF
Parameter
Input Set Up Time to LCLK Rising LCLK Rising to Data Hold Time LCLK Rising to Data Valid LCLK Rising to Active (Float to Active Delay) LCLK Rising to Inactive (Active to Float Delay)
Min
7 0 2 2
Max
Units
ns ns
11 28
ns ns ns
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Table 17: LPC Mode Interface Measurement Condition Parameters
Symbol
VTH VTL VTEST VMAX Input Signal Edge Rate
Value
0.6 VDD 0.2 VDD 0.4 VDD 0.4 VDD 1V/ns
Units
V V V V
Figure 5: Input Timing Parameters
VTH LCLK VTEST VTL TSU TDH LAD[3:0] (Valid Input Data) Valid Inputs VMAX
Figure 6: Output Timing Parameters
VTH LCLK VTEST VTL TVAL LAD[3:0] (Valid Output Data)
LAD[3:0] (Float Output Data) TON TOFF
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Table 18: LPC Mode Interface AC Input/Output Characteristics
Symbol Parameter Test Conditions
0 < VOUT 0.3VDD IOH (AC) Switching Current High (Test Point) IOL (AC) Switching Current Low (Test Point) ICL ICH slewr slewf Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate 0.3VDD < VOUT 0.9VDD 0.7VDD < VOUT VDD VOUT = 0.7VDD VDD > VOUT 0.6VDD 0.6VDD > VOUT > 0.1VDD 0.18VDD > VOUT > 0 VOUT=0.18VDD -3 < VIN -1 VDD+4 > VIN > VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015 1 1 4 4 16VDD 26.7VOUT Equation D 38VDD
Min
-12 VDD -17.1(VDD-VOUT)
Max
Units
mA mA
Equation C -32 VDD
mA mA mA mA mA mA mA mA V/ns V/ns
Notes: 1. See PCI specification. 2. PCI specification output load is used.
Table 19: LPC Mode Interface Reset Timing Parameters, VDD=3.0-3.6V
Symbol
TPRST TKRST TRSTP TRSTF TRST
(1)
Parameter
VDD Stable to Reset Low Clock Stable to Reset Low RST Pulse Width RST Low to Output Float RST High to LFRAME Low RST Low to Reset During Erase or Program RST or INIT Slew Rate
Min
1 100 100
Max
Units
ms
s
ns 48 ns
s s
1 10 50
TRSTE
mV/ns
Notes: 1. There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation.
Figure 7: Reset Timing Diagram
VDD LCLK TKRST RST/INIT TRSTF LAD[3:0] TRSTE TRST
Program or Erase Operation Aborted
TPRST
TRSTP
LFRAME
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Figure 8: A/A Mux Mode AC Input/Output Reference Waveforms
VIHT INPUT VILT AC test inputs are driven at VIHT (0.9VDD) for a logic HIGH and VILT (0.1VDD) for a logic LOW. Measurement reference points for inputs and outputs are VIT (0.5VDD) and VOT (0.5VDD). Input rise and fall times (10% <-> 90%) are < 5ns Note: V IT: VINPUT Test V OT: VOUTPUT Test V IHT: VINPUT HIGH Test V ILT: VINPUT LOW Test VIT Reference Points VOT OUTPUT
Figure 9: A/A Mux Mode Test Load Condition
TO TESTER
TO DUT CL=30pF
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A/A MUX MODE AC CHARACTERISTICS Table 20: Read Cycle Timing Parameters VDD=3.0-3.6V
Symbol
TRC TRST TAS TAH TAA TOE TOLZ TOHZ TOH
Parameter
Read Cycle Time RST High to Row Address Setup R/ C Address Set-up Time R/ C Address Hold Time Address Access Time Output Enable Access Time OE Low to Active Output OE High to High-Z Output Output Hold from Address Change
Min
270 1 45 45
Max
Units
ns
s
ns ns 120 60 ns ns ns 35 ns ns
0 0
Table 21: Program/Erase Cycle Timing Parameters, VDD=3.0-3.6V
Symbol
TRST TAS TAH TCWH TOES TOEH TOEP TOET TWP TWPH TDS TDH TIDA TBP TBE TSCE
Parameter
RST High to Row Address Setup R/ C Address Setup Time R/ C Address Hold Time R/ C to Write Enable High Time OE High Setup Time OE High Hold Time OE to Data Polling Delay OE to Toggle Bit Delay
WE Pulse Width WE Pulse Width High
Min
1 50 50 50 20 20
Max
Units
s
ns ns ns ns ns 40 40 ns ns ns ns ns ns 150 300 8 10 ns
s
100 100 50 5
Data Setup Time Data Hold Time Product ID Access and Exit Time Byte Programming Time Block Erase Time Chip Erase Time
s s
Table 22: Reset Timing Parameters, VDD=3.0-3.6V
Symbol
TPRST TRSTP TRSTF TRST
(1)
Parameter
VDD Stable to Reset Low RST Pulse Width RST Low to Output Float RST High to LFRAME Low
Min
1 100
Max
Units
ms ns
48 1
ns
s s
TRSTE RST Low to Reset During Erase or Program 10 Notes: 1. There will be a reset latency of TRSTE if a reset procedure is performed during a Program or Erase operation.
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Figure 10: A/A Mux Mode Read Cycle Timing Diagram
TRSTP RST
TRST
Row Address
TRC
Column Address Row Address Column Address
Address
TAS R/C VIH
TAH
TAS
TAH
WE
TAA
TOH
OE TOE High-Z TOLZ
Data Valid
TOHZ High-Z
I/O7-I/O0
Figure 11: A/A Mux Mode Write Cycle Timing Diagram
TRSTP RST
TRST
Row Address Column Address
Address
TAS R/C
TAH
TAS
TAH
TCWH OE TOES TWP
TOEH TWPH
WE TDS I/O7-I/O0 High-Z
Data Valid
TDH
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Figure 12: A/A Mux Mode Data Polling Timing Diagram
Row Address Column Address Row Address Column Address Row Address Column Address Row Address Column Address
Address
R/C
WE TOEP OE High-Z
I/O7
Data In
Data#
Data#
Data
Final Input Command
Status Bit
Status Bit
Data
Command Input
Write Operation In Progress
Write Operation Complete
Figure 13: A/A Mux Mode Toggle Bit Timing Diagram
Address
Row Address Column Address Row Address Column Address Row Address Column Address Row Address Column Address
R/C
WE TOET OE High-Z
I/O6
Data In
Data
Final Input Command
Status Bit
Status Bit
Data
Command Input
Write Operation In Progress
Write Operation Complete
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Figure 14: A/A Mux Mode Byte Program Timing Diagram
Four-Byte Byte Program Command Sequence 5555 Address 2AAA 5555 PA
R/C
OE
TWP
TWPH
TBP
WE High-Z
AA 55 A0 PD
I/O7-I/O0
Byte Program Command Input PA = Byte Program Address PD = Byte Program Data
Byte Program Operation In Progress
Figure 15: A/A Mux Mode Block Erase Timing Diagram
Six-Byte Block Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA BA
R/C
OE
TWP TWPH
TBE
WE High-Z
AA 55 80 AA 55 30/50
I/O7-I/O0
Block Erase Command Input BA = Block Address
Block Erase Operation In Progress
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Figure 16: A/A Mux Mode Chip Erase Timing Diagram
Six-Byte Chip Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA 5555
R/C
OE
TWP TWPH
TSCE
WE High-Z
AA 55 80 AA 55 10
I/O7-I/O0
Chip Erase Command Input
Chip Erase Operation In Progress
Figure 17: A/A Mux Mode Product ID Entry and Read Timing Diagram
Three-Byte Product ID Entry Command Sequence 5555 Address 2AAA 5555 0000 0001 0003
R/C
OE
TWP TWPH
TIDA
WE High-Z
AA 55 90 37
TAA
95 7F
I/O7-I/O0
Figure 18: A/A Mux Mode Product ID Exit and Reset Timing Diagram
Three-Byte Product ID Exit and Reset Command Sequence 5555 Address 2AAA 5555
R/C
OE
TWP TWPH
WE High-Z
AA 55 F0
I/O7-I/O0
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Figure 19: Automatic Byte Program Algorithm
Start
Write Command Address: 5555H Data: AAH
Write Command Address: 2AAAH Data: 55H
Write Command Address: 5555H Data: A0H
Write Command Address: PA Data: PD
NO
I/O7 = Data ? Or I/O6 Stop Toggle?
YES
Byte Program Completed
PA: Byte Program Address PD: Byte Program Data
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Figure 20: Automatic Block Erase Algorithm
Start
Write Command Address: 5555H Data: AAH
Write Command Address: 2AAAH Data: 55H
Write Command Address: 5555H Data: 80H
Write Command Address: 5555H Data: AAH
NO
Write Command Address: 2AAAH Data: 55H
I/O7 = Data ? Or I/O6 Stop Toggle?
YES
Write Command Address: BA Data: 30H or 50H
Block Erase Completed
BA: Block Address
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Figure 21: Automatic Chip Erase Algorithm
Start
Write Command Address: 5555H Data: AAH
Write Command Address: 2AAAH Data: 55H
Write Command Address: 5555H Data: 80H
Write Command Address: 5555H Data: AAH
NO
Write Command Address: 2AAAH Data: 55H
I/O7 = Data ? Or I/O6 Stop Toggle?
YES
Write Command Address: 5555H Data: 10H
Chip Erase Completed
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Figure 22: Product ID Command Flowchart
Start
Start
OR
Write Command Address: 5555H Data: AAH
Write Command Address: 5555H Data: AAH
Write Command Address: 2AAAH Data: 55H
Write Command Address: 2AAAH Data: 55H
Write Command Address: 5555H Data: 90H
Write Command Address: 5555H Data: F0H
Write Command Address: XXXXH Data: F0H
Enter Product ID Mode
Exit Product ID Mode
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Ordering Information
A49LF040AT x - 33 F
Package Type
F = Pb-Free
Clock Frequency
33 = 33MHz
Package Type
L = PLCC X = TSOP (8mmX14mm)
Device Number
4 Mbit LPC Flash Memory
Part No.
Clock Frequency (MHz)
Boot Block Location
Top
Temperature Range
0C to +85C
Package Type
A49LF040ATL-33
32-pin PLCC
A49LF040ATL-33F
Top 33 Top Top
0C to +85C 0C to +85C 0C to +85C
32-pin Pb-Free PLCC 32-pin TSOP (8mm X 14 mm) 32-pin Pb-Free TSOP (8mm X 14 mm)
A49LF040ATX-33
A49LF040ATX-33F
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Package Information
PLCC 32L Outline Dimension
unit: inches/mm
HD D 13 5
14
4
32
20
30
21
29
A2
A
HE
1
E
b1 GD y D
A1
e
b
GE
Dimensions in inches
Dimensions in mm Min 0.47 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 0 Nom 2.80 0.71 0.46 0.254 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 Max 3.40 2.93 0.81 0.54 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.075 10
Symbol
A A1 A2 b1 b C D E e GD GE HD HE L y
Min 0.0185 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0
Nom 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 -
Max 0.134 0.115 0.032 0.021 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.003 10
Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only.
PRELIMINARY (March, 2006, Version 0.1)
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AMIC Technology, Corp.
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A49LF040A
Package Information
TSOP 32L TYPE I (8 X 14mm) Outline Dimensions
unit: inches/mm
Pin1
0.254 Gage Plane L Detail "A"
A2
E
D1 D Detail "A"
A1
c
e
b y D
Dimensions in inches Symbol A A1 A2 b c E e D D1 L y Min 0.002 0.037 0.0067 0.004 0.311 0.543 0.484 0.020 0.000 0 Nom 0.039 0.0087 0.315 0.0197 0.551 0.488 0.024 3 Max 0.047 0.006 0.041 0.0106 0.0083 0.319 0.559 0.492 0.028 0.003 5
Dimensions in mm Min 0.05 0.95 0.17 0.10 7.90 13.80 12.30 0.50 0.00 0 Nom 1.00 0.22 8.00 0.50 14.00 12.40 0.60 3 Max 1.20 0.15 1.05 0.27 0.21 8.10 14.20 12.50 0.70 0.076 5
Notes: 1. Dimension E does not include mold flash. 2. Dimension D1 does not include interlead flash. 3. Dimension b does not include dambar protrusion.
PRELIMINARY (March, 2006, Version 0.1)
31
AMIC Technology, Corp.
A

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